ModelSim
Synopsys VCS
Cadence Incisive
Riviera-PRO
gEDA Project
Logisim
VCS
Proteus PCB design
Spendesk
Expensify
Abacus
Fyle
webexpenses
Bill.com
Ariba
Zoho Expense
ModelSimSynopsys VCS - HDL Simulator of System Verilog, Verilog, and VHDL for ASIC design and verification.
Expensify - Import expenses directly from a credit card to create free expense reports quickly. Approve reports online and reimburse directly to a checking account with one click.
Cadence Incisive - System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification
Abacus - Expenses without the 'expense report'
Riviera-PRO - System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs.
Fyle - Track expenses across devices on-the-go and maintain a central repository. With custom approval flows, automatic policy violation detection and an automated audit trail, be audit-ready at all times!