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Synopsys VCS - HDL Simulator of System Verilog, Verilog, and VHDL for ASIC design and verification.
libmv - libmv is a structure from motion library, which plans to one day take raw video footage or...
Cadence Incisive - System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification
ACTS - ACTS is an automatic camera tracking system which can efficiently and stably recover camera motion...
Riviera-PRO - System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs.
gEDA Project - All about General Public License (GPL) and Electronic Design Automation (EDA) software tools