ModelSim
Synopsys VCS
Riviera-PRO
Cadence Incisive
gEDA Project
VCS
Logisim
Proteus PCB design
Task Muncher
Taskable
Motion Firefox
TideTask
TManager
WISP
WorkInSync
Maptician
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Synopsys VCS - HDL Simulator of System Verilog, Verilog, and VHDL for ASIC design and verification.
Taskable - Using multiple work apps leads to tons of context switching, breaking flow and killing productivity.
Riviera-PRO - System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs.
Motion Firefox - All-in-one time management tool in Firefox
Cadence Incisive - System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification
TideTask - Control your procrastination and never miss a task again