ESO Scheduling VS FigJam

Synopsys VCS - HDL Simulator of System Verilog, Verilog, and VHDL for ASIC design and verification.

GEES - GEES is an all-in-one AI design platform that is shaping a future where you can brainstorm, design, hand-off in one file — without changing any other tools.

Riviera-PRO - System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs.

Miro - Scalable, secure, cross-device and enterprise-ready team collaboration tool for distributed teams. Join 2M+ users & 8000+ teams from around the world.

VCS - Workforce management software for police & fire departments

Figma - Team-based interface design, Figma lets you collaborate on designs in real time.